1. Field of the Invention
The present invention relates to a wiring board that is used in mounting electronic components such as semiconductor devices, and an electronic component device.
2. Description of the Related Art
Conventionally, a build-up method has been widely used as a technology to manufacture a wiring board in a multi-layer wiring structure. Various types of wiring boards using the build-up method can be fabricated due to combinations of a material (resin, representatively) of interlayer insulating film and a via hole forming process, and its typical set of manufacturing processes includes forming of insulating layers, forming of via holes in the insulating layers and forming of wiring layers including the inside of the via holes on the both surfaces or one surface of a core board as a supporting base material, and sequentially repeating those steps to build up the layers. Of areas in such a structure, the wiring layers and insulating layers can be formed thin because they are stacked by the build-up method, but the core board requires reasonable thickness to provide the wiring board with rigidity, and thus thin manufacturing of the entire wiring board (semiconductor package) was limited.
Therefore, a structure in which the core board (supporting member) is removed has been recently employed to achieve further thin manufacturing of the wiring board. The wiring board having such structure is also called a “coreless board” which means that the board does not have “core” areas.
As an example of the manufacturing method of such coreless board, a basic process described in Patent Document 1 (Japanese Patent Laid-open No. 2007-158174) will be described. It includes preparing a temporary board as a supporting body, sequentially forming a required number of build-up layers (insulating layers including via holes, wiring layers including the inside of the via holes) in a wiring forming region on the temporary board, afterwards covering the layers with solder resist film, and finally removing an outer periphery region of the wiring forming region by cutting it to remove the temporary board.
Then, it is followed by mounting chips on the coreless board, and afterwards filling underfill resin in gaps between the chips and the coreless board, or covering the entire coreless board with mold resin so as to cover the chips.
As described above, the conventional coreless board (wiring board) has a disadvantage that rigidity of the entire wiring board is small due to no core board, and therefore, “warp” easily occurs in the wiring board.
“Warp” is considered to be caused by a thermal expansion coefficient difference between resin used in an interlayer insulating film or a solder resist layer and a wiring layer, a thermal expansion coefficient difference between semiconductor chips (electronic components) and a wiring board, and furthermore, a thermal expansion coefficient difference between mold resin that covers the entire wiring board after mounting semiconductor chips or underfill resin filled in gaps between semiconductor chips and a wiring board, and be invited by thermal treatment in mounting semiconductor chips, thermal treatment in curing a resin material, or the like.
Then, it was conceived that the rigidity of the entire wiring board was increased by improving an outer periphery region that is a region surrounding the wiring forming region and is removed by cutting it at the time of making finished goods, and forming a dummy pattern (hereinafter, referred to as a “solid dummy pattern”) that covers the entire outer periphery region, is made of the same material as the material of the wiring layer, and is disposed in the same layer as the wiring layer.
On the other hand, it is known that only forming the solid dummy pattern in the outer periphery region is insufficient to reduce the warp of wiring board, and occurrence of the warp of wiring board is considerably influenced by a distribution state of the wiring layer in the wiring forming region and that of the dummy pattern in the outer periphery region not only at a stage before chip mounting but also even after chip mounting.
Then, the following technologies are proposed. They are a technology of providing slits in required areas of the solid dummy pattern in the outer periphery region (Patent Document 2 (Japanese Patent Laid-open No. 2005-167141), a technology of making the area ratio of wiring layer in the wiring forming region (the area ratio of wiring patterns to the entire wiring forming region) substantially equal to the area ratio of dummy pattern in the outer periphery region (the area ratio of dummy pattern to the entire outer periphery region), a technology of using the solid dummy pattern and divided dummy patterns in combination (these technologies are described in Patent Document 3 (Japanese Patent Laid-open No. 2008-21921)), and the like.
However, even by using such technologies, it can be said that the problem of the warp of wiring board before and after chip mounting is not sufficiently solved.